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Espressif Systems /ESP32-S3-ULP /RTC_I2C /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLAVE_TRAN_COMP_INT_ST)SLAVE_TRAN_COMP_INT_ST 0 (ARBITRATION_LOST_INT_ST)ARBITRATION_LOST_INT_ST 0 (MASTER_TRAN_COMP_INT_ST)MASTER_TRAN_COMP_INT_ST 0 (TRANS_COMPLETE_INT_ST)TRANS_COMPLETE_INT_ST 0 (TIME_OUT_INT_ST)TIME_OUT_INT_ST 0 (ACK_ERR_INT_ST)ACK_ERR_INT_ST 0 (RX_DATA_INT_ST)RX_DATA_INT_ST 0 (TX_DATA_INT_ST)TX_DATA_INT_ST 0 (DETECT_START_INT_ST)DETECT_START_INT_ST

Description

interrupt state register

Fields

SLAVE_TRAN_COMP_INT_ST

slave transit complete interrupt state
ARBITRATION_LOST_INT_ST

arbitration lost interrupt state
MASTER_TRAN_COMP_INT_ST

master transit complete interrupt state
TRANS_COMPLETE_INT_ST

transit complete interrupt state
TIME_OUT_INT_ST

time out interrupt state
ACK_ERR_INT_ST

ack error interrupt state
RX_DATA_INT_ST

receive data interrupt state
TX_DATA_INT_ST

transit data interrupt state
DETECT_START_INT_ST

detect start interrupt state

Links

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Register License

Copyright 2023 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data